Semoce EDA
Coming soon
We are building an original EDA suite — and, with it, the silicon for the next generation of intelligent systems.
- Semoce EDA
- agni · synthesis
- sutra · place & route
- kala · timing
- Silicon · next
agni
Built · in testing
sutra
Coming soon
kala
Coming soon
The Semoce EDA suite
From RTL to GDSII — three engines, built from scratch
agni, sutra and kala are original engines in native C++, sharing Liberty libraries and handing off through standard netlist and DEF formats.
Viewers
Native Qt5 viewers ship with the engines: a schematic view for agni and a layout view for sutra, with per-layer visibility.
Read moreScripts
Batch TCL for CI, or an interactive shell by typing the tool name. Familiar commands, JSON reports for pipelines.
Read moreProof
Every engine is checked against an independent reference — iverilog for synthesis, OpenSTA for timing, Magic and Netgen for signoff. We publish what the reference measures, not what we hope.
Read more
The flow
Nine steps. Three engines.
Verilog in, a placed, routed, timing-analysed layout out — on commodity Linux, with no license server.
Start from Verilog RTL — the same source you simulate today.
Technology-independent optimisation, then NPN truth-table mapping to your standard-cell library.
Area, timing and power reports, with a native Qt5 schematic viewer.
Core rows, I/O pins, power grid, well-tap and filler insertion.
Simulated-annealing placement with timing-driven net weights and a strict legality gate.
H-tree clock-tree synthesis and buffer insertion.
Negotiated-congestion detailed routing on a real metal stack, with DEF output.
Slew-aware NLDM delays, SPEF back-annotation, multi-corner analysis, WNS and TNS.
Stream out GDSII, then sign off with Magic DRC and Netgen LVS.
Illustrative output · Semoce EDA is in development
Silicon · on our roadmap
The chips we're building toward
Tools come first. These are the markets our silicon will target once our tools have carried designs to tape-out.
Precise motor control in Robotics.
Deterministic, low-latency control loops for motors and actuators.
Neural accelerators for edge inference.
Low-power NPU silicon: the long-term goal our tools are built for.
Radiation-aware design for Space.
Hardened logic and error-tolerant memory for life in orbit.
Sensor fusion for Autonomous vehicles.
Fusing camera, radar and lidar data in real time.
Always-on chips for Industrial IoT.
Microwatt-class silicon that runs for years on a battery.
Our belief
The next generation of chips will be designed by small, fast teams — if they have the right tools. We are building those tools first, then proving them in silicon.
Built on open standards
Semoce EDA reads and writes the formats engineers already use, and runs on the open process kits — so nothing you build is locked in.
Let's collaborate130SKY130Open PDK
180GF180MCUOpen PDK
VVerilogRTL input
LIBLibertyTiming libraries
DEFLEF / DEFPhysical design
GDSGDSIILayout output
SPFSPEFParasitics
TCLTCLScripting
QTQt5GUI viewers
Support
Contact
Talk to the team about Semoce EDA or your design.
Docs
Guides and command reference for agni, sutra and kala.
FAQ
Quick answers on status, platforms and PDKs.
What is Semoce EDA?
Semoce EDA is our RTL-to-GDSII suite: agni for synthesis, sutra for place & route and kala for static timing. The engines are written from scratch in native C++ — they don't wrap other flows.
When can I use it?
agni is built and in testing now; sutra and kala are in development. Join the waitlist and we'll let you know as each engine is released.
What does it run on?
Linux x86-64. The engines are command-line tools with TCL scripting and an interactive shell; the GUI viewers use Qt5.
Which process technologies are supported?
Semoce EDA targets the open SKY130 and GF180MCU process kits, and reads any standard Liberty, LEF and GDS — so other foundry kits can be plugged in.
Does Semoce make chips?
Not yet. Silicon is the second half of our plan: once Semoce EDA has taken designs to tape-out, we'll use it to build our own chips.