RTL in. GDSII out.
Semoce EDA is an original, from-scratch suite - RTL synthesis, place & route and static timing in native C++. Three engines, one flow, no license server.
agni
Reads Verilog, runs technology-independent optimisation, and maps to your standard-cell library with NPN truth-table matching - not naive operator substitution. Produces a gate-level netlist with timing, area and power reports.
- Input
- Verilog RTL
- Output
- Gate-level netlist
- Viewer
- agni-gui schematic
read_verilog rtl.v elaborate compile_ultra report_timing report_area write_verilog net.v
sutra
Floorplanning, simulated-annealing placement with timing-driven net weights, well-tap and filler insertion, H-tree clock-tree synthesis, and congestion-aware routing on a real metal stack.
- Input
- Netlist · LEF
- Output
- DEF · GDSII
- Viewer
- sutra-gui layout
read_verilog net.v set_pdk sky130 init_floorplan place_design insert_tap_cells clock_tree_synthesis route_design write_gds design.gds
kala
Builds a timing graph from the netlist and propagates slew-aware NLDM delays with pin-specific arcs - reporting worst and total negative slack, Fmax and the critical path.
- Input
- Netlist · Liberty · SPEF
- Reports
- WNS · TNS · Fmax
- Analysis
- Multi-corner PVT
create_clock -period 2000 clk read_spef design.spef update_timing report_timing -nworst 10 report_global_timing
One flow, three engines.
The engines share Liberty libraries and hand off through standard netlist and DEF formats - the same separation of concerns a professional flow uses.
Start from Verilog RTL - the same source you simulate today.
Technology-independent optimisation, then NPN truth-table mapping to your standard-cell library.
Area, timing and power reports, with a native Qt5 schematic viewer.
Core rows, I/O pins, power grid, well-tap and filler insertion.
Simulated-annealing placement with timing-driven net weights and a strict legality gate.
H-tree clock-tree synthesis and buffer insertion.
Negotiated-congestion detailed routing on a real metal stack, with DEF output.
Slew-aware NLDM delays, SPEF back-annotation, multi-corner analysis, WNS and TNS.
Stream out GDSII, then sign off with Magic DRC and Netgen LVS.
Illustrative output · Semoce EDA is in development
Validated, not asserted.
Every engine is measured against an independent reference tool. We'll publish the scorecard - and the scripts to reproduce it - with each release.
Logical equivalence
The RTL and the synthesised netlist are simulated over identical stimulus by an independent simulator, and the traces compared.
Timing correlation
Worst slack and per-stage cell delays are compared against OpenSTA on the same netlist and libraries.
Physical signoff
Layouts are checked with Magic DRC and Netgen LVS on the open PDKs, plus a strict placement legality gate.
If a number wasn't measured, Semoce EDA prints n/a - never zero, never "pass".
- Platform
- Linux x86-64
- Implementation
- Native C++17
- Input / output
- Verilog → DEF / GDSII
- Process kits
- SKY130 · GF180MCU
- Interfaces
- CLI · TCL · Qt5 GUI
- Libraries
- Any Liberty / LEF
Read the docs.
Getting started, the command reference for agni, sutra and kala, file formats and process kits - growing with every release.
Open the docs →# synth.tcl - a first agni session read_verilog design.v elaborate top compile_ultra report_area report_timing write_verilog design_net.v # run it $ agni -f synth.tcl # or explore interactively $ agni agni> help
Be first to run Semoce EDA.
We're opening agni to early testers first, then sutra and kala.