agni: synthesis

Built · in testing

agni turns Verilog RTL into a gate-level netlist mapped onto a standard-cell library. It runs as a batch script (agni -f synth.tcl) or as an interactive shell (agni).

• SAT-based equivalence check of the gate netlist against the RTL
• Broad Verilog-2005 support: 125 of 126 equivalence tests pass; reads the full PicoRV32 RISC-V core
• Clock gating, set_driving_cell, DFT scan insertion

Read the design

Select the process kit, load the cell library, then read your Verilog. Read every source file before elaborating.

set_pdk sky130
read_builtin_lib sky130
read_verilog design.v
read_verilog blocks.v

To use your own Liberty file instead of the built-in SKY130 library, read it with read_liberty:

read_liberty my_cells.lib

Set the top module

elaborate builds the design hierarchy from the top module and reports its cells, nets and ports. check_design then looks for undriven wires, floating outputs, inferred latches, multi-driven nets and missing constraints.

elaborate top
check_design

Constraints

Define clocks and I/O timing before synthesis so optimisation has a target. Read an SDC file or type the commands directly.

create_clock -name clk -period 2000 [get_ports clk]
set_input_delay  -max 200 -clock clk [all_inputs]
set_output_delay -max 200 -clock clk [all_outputs]
set_false_path -from [get_ports rst_n]
set_driving_cell -lib_cell sky130_fd_sc_hd__buf_2 [get_ports din]
set_load 5 [get_ports dout]
set_max_fanout 8
set_max_transition 150

set_driving_cell models the gate that drives an input port, so input transition times are realistic. set_load sets the capacitance on an output port in femtofarads.

Synthesize and map

compile runs standard-effort synthesis and compile_ultra runs high effort. Both optimise the logic (constant propagation, dead-code removal, shared subexpressions) and map it onto library cells by truth-table matching.

read_sdc constraints.sdc
compile_ultra

To run the technology-independent optimisation on its own, use optimize_logic. A later compile -incremental reoptimises without starting over.

Clock gating

insert_clock_gates finds registers loaded through an enable multiplexer and replaces the multiplexer with an integrated clock-gating cell, cutting dynamic power. Use -dry_run first to list candidates without changing the netlist.

insert_clock_gates -dry_run
insert_clock_gates -cell sky130_fd_sc_hd__dlclkp_1

DFT scan insertion

insert_scan swaps flip-flops for their scan variants, stitches them into a scan chain and adds scan_in, scan_out and scan_enable ports. The library must contain scan flip-flops.

insert_scan

Equivalence check

Save the design before synthesis with set_golden, synthesize, then run run_lec. agni checks the gate netlist against the saved RTL with a SAT-based equivalence check and reports any mismatching outputs.

elaborate top
read_sdc constraints.sdc
set_golden
compile_ultra
run_lec

Reports

report_timing -nworst 5 -max_paths 5
report_power -activity 0.2

Write the results

write_verilog design_net.v
write_sdc design.sdc

The netlist and constraints feed straight into sutra and kala.

Schematic viewer

agni-gui opens the synthesized netlist as a schematic, so you can follow a path cell by cell. It needs Qt5 and is built automatically when Qt5 is installed.