Semoce EDA is an RTL-to-GDSII suite written from scratch in C++. Three engines share Liberty libraries and hand off through standard files, so each one can run on its own or as part of a single flow.
The flow
A design moves through nine steps. Constraints come first, because synthesis, placement and timing all depend on them.
- RTL and constraintsVerilog source plus SDC-style constraints: clocks, I/O delays, exceptions.
- Synthesis agniTechnology-independent optimisation, then mapping to your standard-cell library.
- Checks agniEquivalence check of the gate netlist against the RTL, area and timing reports, and a Qt5 schematic viewer.
- Floorplan sutraCore rows, I/O pins, power grid, well-tap and filler insertion.
- Placement sutraAnalytic quadratic seed, density spreading and annealing refinement, routability-driven by default, then Abacus legalization with a strict legality check.
- Clock tree sutraMulti-level buffered clock tree: sinks clustered by balanced geometric bisection, each buffer sized for its load from the Liberty tables.
- Routing sutraA* global routing, then negotiated-congestion detailed routing on the real metal stack, with via optimization, antenna repair and DEF output.
- Timing kalaSlew-aware NLDM delays with SPEF back-annotation, multi-mode multi-corner (MMMC) analysis, CRPR, crosstalk-aware timing windows, path groups, WNS and TNS.
- GDSII sutraStream out GDSII for DRC and LVS signoff with Magic and Netgen.
How the engines talk
Each engine is a standalone Linux binary with a TCL interpreter. Run a script in batch mode with -f, or start the binary on its own for an interactive shell. The engines exchange standard files, so you can stop after any step and pick up later.
| Engine | Reads | Writes |
|---|---|---|
| agni | Verilog, Liberty, SDC | Gate-level Verilog netlist, SDC |
| sutra | Gate-level netlist, LEF, Liberty, SDC | DEF, SPEF, GDSII |
| kala | Gate-level netlist, Liberty, SPEF, SDC | Timing reports |
How results are checked
agni is checked against iverilog simulation and a SAT-based equivalence check on every design. kala correlation against OpenSTA and Magic DRC / Netgen LVS signoff run in our test campaign; we publish those numbers when they are measured, not before.
Where to go next
- Installation covers system requirements and building on Linux.
- Quick start runs one complete RTL-to-GDSII flow.
- Command reference lists every documented command and option.