Command reference | Semoce EDA Documentation

Every command, option and example on this page is checked against the engines' command table when the docs are built. Commands are grouped by the engine you will usually run them in; the common commands work in all three.

Common: design, library and constraints

These commands work in all three engines.

`set_pdk`

Select a process kit profile (for example sky130).

Synopsis

set_pdk &lt;key&gt;

Example

set_pdk sky130

`read_builtin_lib`

Load the built-in standard-cell library for a process kit.

Synopsis

read_builtin_lib &lt;pdk&gt;

Example

read_builtin_lib sky130

`read_verilog`

Read Verilog RTL or a gate-level netlist.

Synopsis

read_verilog &lt;file.v&gt;

Example

read_verilog design.v

`read_liberty`

Read a Liberty cell library.

Synopsis

read_liberty &lt;file.lib&gt;

Example

read_liberty my_cells.lib

`read_lef`

Read LEF technology and cell geometry.

Synopsis

read_lef &lt;file.lef&gt;

Example

read_lef sky130_fd_sc_hd.lef

`read_sdc`

Read constraints from an SDC file.

Synopsis

read_sdc &lt;file.sdc&gt;

Example

read_sdc constraints.sdc

`set_top_module`

Set the top-level module.

Synopsis

set_top_module &lt;name&gt;

Example

set_top_module top

`create_clock`

Define a clock and its period in picoseconds.

Synopsis

create_clock -name &lt;n&gt; -period &lt;ps&gt; [get_ports &lt;port&gt;]

Option	Meaning
`-name <n>`	Clock name
`-period <ps>`	Clock period in picoseconds

Example

create_clock -name clk -period 2000 [get_ports clk]

`create_generated_clock`

Define a clock derived from another, such as a divider output.

Synopsis

create_generated_clock -name &lt;n&gt; -source &lt;clk&gt; [-divide_by &lt;N&gt;] [-multiply_by &lt;M&gt;] [-invert] [get_ports &lt;port&gt;]

Option	Meaning
`-name <n>`	Clock name
`-source <clk>`	Master clock
`-divide_by <N>`	Divide the master frequency
`-multiply_by <M>`	Multiply the master frequency
`-invert`	Invert the generated clock

Example

create_generated_clock -name clk_div2 -source clk -divide_by 2 [get_ports clk_div2]

`set_input_delay`

Set the arrival time of input ports relative to a clock.

Synopsis

set_input_delay -max &lt;ps&gt; -clock &lt;clk&gt; [get_ports &lt;p&gt;]

Option	Meaning
`-max <ps>`	Delay in picoseconds
`-clock <clk>`	Reference clock

Example

set_input_delay -max 200 -clock clk [all_inputs]

`set_output_delay`

Set the required time of output ports relative to a clock.

Synopsis

set_output_delay -max &lt;ps&gt; -clock &lt;clk&gt; [get_ports &lt;p&gt;]

Option	Meaning
`-max <ps>`	Delay in picoseconds
`-clock <clk>`	Reference clock

Example

set_output_delay -max 200 -clock clk [all_outputs]

`set_clock_uncertainty`

Add clock uncertainty (jitter and skew margin) in picoseconds.

Synopsis

set_clock_uncertainty &lt;ps&gt; [get_clocks &lt;clk&gt;] [-setup] [-hold]

Option	Meaning
`-setup`	Apply to setup checks only
`-hold`	Apply to hold checks only

Example

set_clock_uncertainty 50 [get_clocks clk]

`set_false_path`

Exclude paths from timing analysis.

Synopsis

set_false_path [-from &lt;f&gt;] [-to &lt;t&gt;]

Option	Meaning
`-from <f>`	Start points
`-to <t>`	End points

Example

set_false_path -from [get_ports rst_n]

`set_multicycle_path`

Allow a path more than one clock cycle.

Synopsis

set_multicycle_path &lt;n&gt; [-from &lt;f&gt;] [-to &lt;t&gt;]

Option	Meaning
`-from <f>`	Start points
`-to <t>`	End points

Example

set_multicycle_path 2 -from [get_cells u_div*]

`set_clock_groups`

Declare clocks that are asynchronous to each other.

Synopsis

set_clock_groups -asynchronous -group {clks} -group {clks}

Option	Meaning
`-asynchronous`	The groups never time against each other
`-group {clks}`	One group of clocks; repeat for each group

Example

set_clock_groups -asynchronous -group {clk_a} -group {clk_b}

`set_driving_cell`

Model the cell that drives input ports.

Synopsis

set_driving_cell -lib_cell &lt;cell&gt; [get_ports &lt;port&gt;]

Option	Meaning
`-lib_cell <cell>`	Library cell that drives the port

Example

set_driving_cell -lib_cell sky130_fd_sc_hd__buf_2 [get_ports din]

`set_load`

Set the capacitive load on output ports, in femtofarads.

Synopsis

set_load &lt;fF&gt; [get_ports &lt;port&gt;]

Example

set_load 5 [get_ports dout]

`write_sdc`

Write the active constraints to an SDC file.

Synopsis

write_sdc [file.sdc]

Example

write_sdc design.sdc

`help`

Show help for one command or list all commands.

Synopsis

help [command]

Example

help create_clock

agni: synthesis

`elaborate`

Build the design hierarchy from the top module and report its size.

Synopsis

elaborate [&lt;top_module&gt;]

Example

elaborate top

`check_design`

Check for undriven wires, floating outputs, latches, multi-driven nets and missing constraints.

Synopsis

check_design

Example

check_design

`compile`

Run standard-effort synthesis.

Synopsis

compile [-incremental]

Option	Meaning
`-incremental`	Reoptimise the current netlist without starting over

Example

compile

`compile_ultra`

Run high-effort synthesis.

Synopsis

compile_ultra [-no_retime] [-physical]

Option	Meaning
`-no_retime`	Do not move registers
`-physical`	Use placement-aware optimisation

Example

compile_ultra

`optimize_logic`

Run technology-independent logic optimisation on its own.

Synopsis

optimize_logic [-no_const_prop] [-no_dce] [-no_cse] [-passes &lt;n&gt;]

Option	Meaning
`-no_const_prop`	Skip constant propagation
`-no_dce`	Skip dead-code removal
`-no_cse`	Skip shared-subexpression removal
`-passes <n>`	Number of passes

Example

optimize_logic -passes 2

`insert_clock_gates`

Replace enable multiplexers in front of registers with clock-gating cells.

Synopsis

insert_clock_gates [-cell &lt;icg_cell&gt;] [-dry_run]

Option	Meaning
`-cell <icg_cell>`	Clock-gating cell to use
`-dry_run`	List candidates without changing the netlist

Example

insert_clock_gates -dry_run

`insert_scan`

Replace flip-flops with scan flip-flops and stitch them into a scan chain.

Synopsis

insert_scan

Example

insert_scan

`set_golden`

Save the current design as the reference for the equivalence check.

Synopsis

set_golden

Example

set_golden

`run_lec`

Check the current netlist against the saved reference.

Synopsis

run_lec

Example

run_lec

`report_area`

Report cell area.

Synopsis

report_area

Example

report_area

`report_qor`

Report a quality-of-results summary.

Synopsis

report_qor

Example

report_qor

`report_power`

Estimate leakage, internal and switching power.

Synopsis

report_power [-activity &lt;α&gt;] [-voltage &lt;V&gt;] [-temp &lt;C&gt;]

Option	Meaning
`-activity <a>`	Switching activity factor
`-voltage <V>`	Supply voltage
`-temp <C>`	Temperature in degrees Celsius

Example

report_power -activity 0.2

`report_registers`

List every flip-flop and latch.

Synopsis

report_registers

Example

report_registers

`write_verilog`

Write the gate-level netlist.

Synopsis

write_verilog [file.v]

Example

write_verilog design_net.v

sutra: place and route

`run_flow`

Run synthesis, floorplan, placement, clock tree, routing and timing in one command, using the loaded design and constraints.

Synopsis

run_flow

Example

run_flow

`init_floorplan`

Create the die, core and placement rows.

Synopsis

init_floorplan [-utilization &lt;f&gt;] [-die_width &lt;w&gt;] [-die_height &lt;h&gt;]

Option	Meaning
`-utilization <f>`	Target core utilization, from 0 to 1
`-die_width <w>`	Die width in micrometres
`-die_height <h>`	Die height in micrometres

Example

init_floorplan -utilization 0.6

`create_power_plan`

Create the VDD and VSS rings and stripes.

Synopsis

create_power_plan [-ring_width &lt;µm&gt;] [-stripe_width &lt;µm&gt;] [-stripe_pitch &lt;µm&gt;] [-ring_layer &lt;n&gt;] [-stripe_layer &lt;n&gt;] [-nets &lt;VDD VSS&gt;]

Option	Meaning
`-ring_width <um>`	Ring width
`-stripe_width <um>`	Stripe width
`-stripe_pitch <um>`	Distance between stripes
`-ring_layer <n>`	Metal layer for the rings
`-stripe_layer <n>`	Metal layer for the stripes
`-nets <VDD VSS>`	Power and ground net names

Example

create_power_plan -ring_width 2.0 -stripe_width 1.0 -stripe_pitch 10.0

`insert_tap_cells`

Place well-tap cells across every row on a fixed pitch.

Synopsis

insert_tap_cells [-cell &lt;tapcell&gt;] [-endcap &lt;cell&gt;] [-distance &lt;um&gt;] [-no_alternate] [-prefix &lt;pfx&gt;]

Option	Meaning
`-cell <tapcell>`	Tap cell to use
`-endcap <cell>`	End-cap cell for the row ends
`-distance <um>`	Tap pitch in micrometres
`-no_alternate`	Do not offset alternate rows
`-prefix <pfx>`	Instance name prefix

Example

insert_tap_cells -distance 13

`place_design`

Place the standard cells (routability-driven by default) and legalize them.

Synopsis

place_design [-effort &lt;1-3&gt;] [-seed &lt;n&gt;]

Option	Meaning
`-effort <1-3>`	Placement effort
`-seed <n>`	Random seed, for reproducible runs

Example

place_design -effort 2

`place_opt`

Place the design, then optimise timing.

Synopsis

place_opt [-effort &lt;1-3&gt;]

Option	Meaning
`-effort <1-3>`	Placement effort

Example

place_opt

`clock_tree_synthesis`

Build and buffer the clock tree.

Synopsis

clock_tree_synthesis

Example

clock_tree_synthesis

`optimize_cts`

Balance the clock tree after it is built.

Synopsis

optimize_cts [-max_skew &lt;ps&gt;] [-max_latency &lt;ps&gt;] [-verbose]

Option	Meaning
`-max_skew <ps>`	Skew target
`-max_latency <ps>`	Latency limit
`-verbose`	Print details

Example

optimize_cts -max_skew 80

`route_design`

Run global and detailed routing.

Synopsis

route_design [-layers &lt;n&gt;] [-max_ripup &lt;n&gt;] [-no_detail]

Option	Meaning
`-layers <n>`	Number of routing layers to use
`-max_ripup <n>`	Rip-up and reroute iterations
`-no_detail`	Stop after global routing

Example

route_design

`optimize_route`

Reroute congested nets after routing.

Synopsis

optimize_route [-iters &lt;n&gt;] [-overflow_threshold &lt;f&gt;] [-verbose]

Option	Meaning
`-iters <n>`	Iterations
`-overflow_threshold <f>`	Overflow level that triggers a reroute
`-verbose`	Print details

Example

optimize_route -iters 5

`optimize_vias`

Add redundant via cuts on critical routes.

Synopsis

optimize_vias [-max_vias &lt;n&gt;] [-verbose]

Option	Meaning
`-max_vias <n>`	Maximum vias to change
`-verbose`	Print details

Example

optimize_vias

`check_antenna`

Report nets that exceed the per-layer antenna ratio limits.

Synopsis

check_antenna [-limit_m1 &lt;r&gt;] [-limit_m2 &lt;r&gt;] [-limit_upper &lt;r&gt;]

Option	Meaning
`-limit_m1 <r>`	Ratio limit on metal 1
`-limit_m2 <r>`	Ratio limit on metal 2
`-limit_upper <r>`	Ratio limit on upper layers

Example

check_antenna

`opt_design`

Optimise timing at a given stage of the flow.

Synopsis

opt_design [-pre_place] [-in_place] [-post_place] [-post_route] [-hold] [-setup]

Option	Meaning
`-pre_place`	Before placement
`-in_place`	During placement
`-post_place`	After placement
`-post_route`	After routing
`-setup`	Fix setup timing
`-hold`	Fix hold timing

Example

opt_design -post_route -setup

`insert_fillers`

Fill the gaps between cells with filler and decap cells.

Synopsis

insert_fillers [-cell &lt;type&gt;] [-prefix &lt;pfx&gt;]

Option	Meaning
`-cell <type>`	Filler cell to use
`-prefix <pfx>`	Instance name prefix

Example

insert_fillers

`report_ir_drop`

Estimate supply voltage droop across the die.

Synopsis

report_ir_drop [-vdd &lt;V&gt;] [-grid &lt;n&gt;] [-threshold &lt;mV&gt;] [-freq &lt;MHz&gt;]

Option	Meaning
`-vdd <V>`	Supply voltage
`-grid <n>`	Analysis grid size
`-threshold <mV>`	Report tiles above this drop
`-freq <MHz>`	Operating frequency

Example

report_ir_drop -vdd 1.8

`report_congestion`

Report routing demand against capacity.

Synopsis

report_congestion [-grid &lt;n&gt;] [-layers &lt;n&gt;]

Option	Meaning
`-grid <n>`	Analysis grid size
`-layers <n>`	Layers to include

Example

report_congestion

`extract_parasitics`

Extract wire resistance and capacitance from the routes.

Synopsis

extract_parasitics [-effort low|medium|high] [-si | -no_si]

Option	Meaning
`-effort low\|medium\|high`	Extraction effort
`-si`	Include crosstalk coupling
`-no_si`	Exclude crosstalk coupling

Example

extract_parasitics -si

`write_def`

Write the placed and routed design as DEF.

Synopsis

write_def [file.def]

Example

write_def design.def

`write_spef`

Write the extracted parasitics as SPEF.

Synopsis

write_spef [file.spef]

Example

write_spef design.spef

`write_gds`

Write the layout as GDSII.

Synopsis

write_gds [file.gds] [-design &lt;name&gt;]

Option	Meaning
`-design <name>`	Top cell name in the GDSII file

Example

write_gds design.gds

`write_layout_html`

Write a self-contained HTML view of the layout.

Synopsis

write_layout_html [file.html]

Example

write_layout_html layout.html

kala: static timing

`read_spef`

Back-annotate wire parasitics from SPEF.

Synopsis

read_spef &lt;file.spef&gt;

Example

read_spef design.spef

`read_mmmc`

Load analysis views (modes and corners) from a view file.

Synopsis

read_mmmc &lt;file.mmmc&gt;

Example

read_mmmc views.mmmc

`update_timing`

Propagate arrival and required times through the design.

Synopsis

update_timing

Example

update_timing

`report_timing`

Report the worst timing paths.

Synopsis

report_timing [-nworst &lt;n&gt;] [-max_paths &lt;n&gt;] [-through &lt;obj&gt;] [-delay min|max]

Option	Meaning
`-nworst <n>`	Number of paths to report
`-max_paths <n>`	Maximum paths per endpoint
`-through <obj>`	Only paths through these nets or pins
`-delay min\|max`	Report hold (min) or setup (max) paths

Example

report_timing -delay min -nworst 5

`report_timing_summary`

Report a one-page timing summary.

Synopsis

report_timing_summary [-max_paths &lt;n&gt;]

Option	Meaning
`-max_paths <n>`	Paths to include

Example

report_timing_summary

`report_global_timing`

Report WNS and TNS for the whole design.

Synopsis

report_global_timing

Example

report_global_timing

`report_wns`

Report the worst negative slack.

Synopsis

report_wns

Example

report_wns

`report_tns`

Report the total negative slack.

Synopsis

report_tns

Example

report_tns

`group_path`

Define a path group for reporting and optimisation.

Synopsis

group_path -name &lt;n&gt; [-from &lt;sp&gt;] [-to &lt;ep&gt;] [-weight &lt;w&gt;] [-critical_range &lt;ps&gt;]

Option	Meaning
`-name <n>`	Group name
`-from <sp>`	Start points
`-to <ep>`	End points
`-weight <w>`	Optimisation weight
`-critical_range <ps>`	Also optimise paths within this range of the worst

Example

group_path -name reg2reg -from [all_registers] -to [all_registers]

`get_path_groups`

List the defined path groups.

Synopsis

get_path_groups [&lt;pattern&gt;]

Example

get_path_groups

`report_mmmc`

Report timing for every mode and corner.

Synopsis

report_mmmc [-verbose]

Option	Meaning
`-verbose`	Show the full cross-view table

Example

report_mmmc -verbose

`report_crpr`

Apply common clock path pessimism removal and report corrected WNS and TNS.

Synopsis

report_crpr

Example

report_crpr

`report_si`

Report crosstalk delay impact.

Synopsis

report_si [-verbose]

Option	Meaning
`-verbose`	Print per-net details

Example

report_si

`report_clock_skew`

Report clock skew against the target.

Synopsis

report_clock_skew [-clock &lt;clk&gt;]

Option	Meaning
`-clock <clk>`	Clock to report

Example

report_clock_skew