Semoce EDA uses the same open formats as the rest of the industry, so you can bring your own libraries and take your results to other tools.
| Format | What it holds | agni | sutra | kala |
|---|---|---|---|---|
| Verilog | RTL source and gate-level netlists | Reads RTL, writes netlist | Reads netlist, writes netlist | Reads netlist |
| Liberty (.lib) | Cell timing, power and area tables | Reads | Reads | Reads |
| LEF | Technology layers and cell geometry | Reads | ||
| DEF | Placed and routed designs | Reads and writes | ||
| SPEF | Extracted wire parasitics | Writes | Reads | |
| SDC | Clocks, I/O delays and timing exceptions | Reads and writes | Reads | Reads |
| GDSII | Final layout for manufacturing | Writes | ||
| JSON reports | Machine-readable results for scripts and CI | Writes | Writes | Writes |
Verilog
agni reads Verilog-2005 RTL with read_verilog and writes the mapped netlist with write_verilog. sutra and kala read that netlist back with read_verilog.
Liberty
Liberty libraries describe each cell's timing arcs (NLDM tables), power and area. Load one with read_liberty, or use the built-in SKY130 library with read_builtin_lib sky130.
LEF and DEF
LEF describes the metal stack and each cell's outline and pins; read it with read_lef. DEF holds a placed or routed design; sutra writes it with write_def and reads it back with read_def.
SPEF
After routing, extract_parasitics computes wire resistance and capacitance and write_spef saves them. kala reads them with read_spef for post-route timing.
SDC
Constraints can be typed as commands or kept in an SDC file and read with read_sdc. write_sdc writes the active constraints so the next engine reads exactly the same ones.
GDSII
write_gds streams the final layout: cell placements, routing and power. It is the file you hand to DRC and LVS signoff.
Reports
Every engine prints human-readable reports to the console. report_flow_json writes the run's results as JSON for scripts and continuous integration, and write_html_report writes a single-file HTML summary.