sutra: place and route

In development Routes small and medium designs today; large-design routing in progress.

sutra turns a gate-level netlist into a placed and routed layout on the real metal stack. It runs as a batch script (sutra -f pnr.tcl) or an interactive shell (sutra).

• One-command run_flow from RTL to GDSII
• Routability-driven placement, A* global routing, negotiated detailed routing
• Via optimization, antenna repair, pin-access analysis
• Timing optimization after placement and after routing (place_opt, opt_design -post_route)
• Power grid with IR-drop analysis, well taps and fillers

Load the netlist

set_pdk sky130
read_builtin_lib sky130
read_lef sky130_fd_sc_hd.lef
read_verilog design_net.v
set_top_module top
read_sdc design.sdc

Read the constraints from agni so placement and optimisation work toward the same clock.

Floorplan

init_floorplan sizes the die and core from a target utilization and creates the placement rows. To give exact dimensions, pass -die_width and -die_height in micrometres, or use create_floorplan with explicit die and core areas.

init_floorplan -utilization 0.6
report_floorplan

Power grid

create_power_plan builds the VDD and VSS rings and stripes.

create_power_plan -ring_width 2.0 -stripe_width 1.0 -stripe_pitch 10.0

Well taps and fillers

Insert well taps right after the floorplan, while the rows are empty, so they land on an exact pitch. Fillers go in after routing to close the gaps between cells.

insert_tap_cells -distance 13
insert_fillers

Placement

place_design starts from an analytic quadratic seed, spreads cells to the density target, refines with annealing and finishes with Abacus legalization and a strict legality check. Placement is routability-driven by default. -effort trades runtime for quality and -seed makes a run reproducible.

read_sdc design.sdc
place_design -effort 2
report_placement
report_congestion

place_opt runs placement followed by timing optimisation.

Clock tree

clock_tree_synthesis builds a multi-level buffered clock tree: sinks are clustered by balanced geometric bisection and each buffer is sized for its load from the Liberty tables. optimize_cts then balances the tree toward a skew target.

clock_tree_synthesis
optimize_cts -max_skew 80
report_clock_skew

Routing

route_design runs A* global routing, then negotiated-congestion detailed routing on the real metal stack. Detailed routing treats power rails and cell metal as blockage.

read_sdc design.sdc
route_design
optimize_route -iters 5
report_route_status

Vias and antennas

optimize_vias adds redundant cuts on critical routes for yield and electromigration headroom. sutra repairs antenna violations during routing; check_antenna reports any net that still exceeds the per-layer ratio limits.

optimize_vias
check_antenna

Timing optimisation

Run optimisation after placement and again after routing, when real wire parasitics are known.

opt_design -post_place -setup
opt_design -post_route -setup
opt_design -post_route -hold

IR drop

report_ir_drop estimates the supply droop across the die from cell power density and grid resistance.

report_ir_drop -vdd 1.8

Write the layout

extract_parasitics
write_def design.def
write_spef design.spef
write_gds design.gds

The SPEF file carries the extracted parasitics to kala; the GDSII file goes to DRC and LVS signoff.

Layout viewer

sutra-gui design.def opens the layout with per-layer visibility. write_layout_html writes a self-contained HTML view you can share without installing anything.

write_layout_html layout.html