Quick start | Semoce EDA Documentation

One complete RTL-to-GDSII run, first with a single command and then step by step through agni, sutra and kala.

This guide takes one small synchronous design from Verilog to a GDSII layout on SKY130. It assumes a file design.v whose top module is top with a clock port clk. Replace the names with your own.

Constraints come first. Every flow below defines the clock with create_clock and the I/O timing before any synthesis, placement or timing command runs. Without them the engines have no timing target.

Write the constraints

Keep constraints in their own file so every engine reads the same ones.

constraints.sdc

create_clock -name clk -period 2000 [get_ports clk]
set_input_delay  -max 200 -clock clk [all_inputs]
set_output_delay -max 200 -clock clk [all_outputs]
set_clock_uncertainty 50 [get_clocks clk]

Periods and delays are in picoseconds: a 2000 ps period is a 500 MHz target.

Option 1: one command

run_flow runs synthesis, floorplan, placement, clock tree, routing and timing in one go, using the design and constraints already loaded.

flow.tcl

set_pdk sky130
read_builtin_lib sky130
read_verilog design.v
elaborate top
read_sdc constraints.sdc
run_flow

sutra -f flow.tcl

Option 2: step by step

Running the engines one at a time lets you inspect each stage and change settings between them.

1. Synthesis with agni

synth.tcl

set_pdk sky130
read_builtin_lib sky130
read_verilog design.v
elaborate top
read_sdc constraints.sdc
check_design
set_golden
compile_ultra
run_lec
report_area
report_timing -nworst 5
write_verilog design_net.v
write_sdc design.sdc

agni -f synth.tcl

set_golden saves the elaborated design before synthesis; run_lec then checks the gate netlist against it.

2. Place and route with sutra

pnr.tcl

set_pdk sky130
read_builtin_lib sky130
read_verilog design_net.v
set_top_module top
read_sdc design.sdc
init_floorplan -utilization 0.6
create_power_plan
insert_tap_cells
place_design
clock_tree_synthesis
route_design
optimize_vias
check_antenna
insert_fillers
extract_parasitics
write_def design.def
write_spef design.spef
write_gds design.gds

sutra -f pnr.tcl

3. Timing with kala

sta.tcl

set_pdk sky130
read_builtin_lib sky130
read_verilog design_net.v
set_top_module top
read_sdc design.sdc
read_spef design.spef
update_timing
report_timing -nworst 10
report_wns
report_tns

kala -f sta.tcl

Look at the result

sutra-gui design.def opens the placed and routed layout.
agni-gui opens the synthesized netlist as a schematic.
design.gds is ready for DRC and LVS with Magic and Netgen.